1. Field Of The Invention
The present invention generally relates to voltage regulators for very large scale integrated (VLSI) circuits, such as dynamic random access memories (DRAMs), static random access memories (SRAMs), and logic circuits, having multi-voltage capability and, more particularly, to a voltage regulator bypass circuit triggered by detection of an onset of an over voltage condition to provide a shunt path to the internal chip capacitance.
2. Background Description
The shrinking of metal. oxide semiconductor field effect transistor (MOSFET) dimensions used in advanced integrated circuit technology for constructing a high circuit density and achieving performance objectives has required reduced power supply voltages. With increased interest in portability, reduced power consumption in complementary metal oxide semiconductor (CMOS) circuits is an important issue. Because power consumption is a function of CV.sup.2 f, the focus has been on reducing both capacitance, C, and power supply voltage, V, as the transition frequency, f, increases. As a result, dielectric thickness continues to be scaled with the power supply voltage. Power supply reduction continues to be the trend of future low voltage CMOS device scaling in advanced semiconductors. The effect of MOSFET scaling on electrostatic discharge (ESD) protection has manifested itself in three ways: the shrinking of ESD structures and input/output (I/O) circuitry, mixed voltage interface (MVI) chips, and noise isolation versus over voltage tradeoffs.
Today's computer architecture also requires the interfacing of semiconductor chip or subsystems with different internal power supply voltages. The semiconductor chip power supply voltages re different because of the technology generation mix, technology types, and applications. DRAM chips, whose geometrical dimensions are typically the most aggressive, must communicate with other logic and microprocessors. With the mix of power supply voltages, chip-to-chip interface I/O circuitry must be designed to avoid electrical over stress and prevent undesirable current leakage paths that create system level power loss. Lower power supply voltages are driving new bus architectures to isolate peripheral noise from internal core logic.
DRAMs, SRAMs and VLSI logic circuits having multi-voltage compatibility use voltage regulators to lower the externally supplied rail voltage to an internal rail voltage. For example, such circuits may have multiple internal rails for 3 V or 5 V, where the externally supplied voltage Vcc is 5 V and a voltage regulator is used to lower this voltage to 3 V for the internal supply voltage Vdd. For 3.3 V/2.5 V systems, the external power Vcc is at 3.3 V and 2.5 V Vdd is defined by the regulator circuit.
ESD networks are typically connected to the external power rail Vcc using diode-based ESD networks. The internal power rail Vdd is biased by the Vcc power rail. In an over voltage event (electrical over-stress (EOS) or electrical discharge (ESD)), the current flows to the Vcc power supply. Since the capacitance of the Vcc power rail is small (on the order of a nano Farad (nF) or less), the Vcc power rail is charged to a high voltage.
In this process, multiple problems can occur. First, the I/O circuitry over voltage destruction occurs. The I/O circuitry MOSFET source and drain electrically overload because of MOSFET secondary breakdown. In receiver structures, the MOSFET gate dielectric is ruptured due to dielectric thermal breakdown. These processes are well understood. In the development of a 16 megabyte (MB) DRAM, a p-type, p-channel MOSFET regulator circuit was used and placed between the Vcc and Vdd power rails. It was discovered by the inventor of the invention described herein that the I/O driver ESD robustness results were low. The I/O circuitry n-channel MOSFET source and drain electrically overloaded because of MOSFET secondary breakdown. The electrical overload occurred since the electrical current could not flow from the Vcc power rail to the Vdd power rail. The p-channel MOSFET source implant did not forward bias since the n-well of the p-channel MOSFET was connected to the Vcc power rail. The Vdd power rail was preferred since it has a large capacitance to the chip substrate ground plane. Hence, a desired solution to establish a function of the regulator to allow current to bypass in an EOS/ESD event.
A second issue is the over voltage of the voltage regulator circuit itself. In the development of a 16 MB DRAM, an n-type, n-channel MOSFET regulator circuit was used and placed between the Vcc and Vdd power rails. In the simulated human body model (HBM) positive ESD test impulse mode, the inventor of the invention described herein discovered the n-channel transistor of the voltage regulator was destroyed due to electrical overload. The electrical overload occurred since the electrical current flowed from the Vcc power rail to the internal Vdd power rail. The Vdd power rail was preferred since it has a large capacitance to the chip substrate ground plane. To prevent the electrical overload of the voltage regulator circuit, the ESD requirements may force the normal operational function of the n-channel transistor to be much larger than desired for function operations due to both current drive and physical space. Hence, a desired solution to prevent MOSFET secondary breakdown in the voltage regulator is necessary. Further, a desired solution to establish a function of the regulator to allow current to bypass in an EOS/ESD event and prevent electrical destruction of the voltage regulator critical circuits. A second electrical over stress impulse is a charge device model (CDM) impulse. A solution is needed to allow current to pass from the Vdd power rail to the Vcc power rail to the output nodes. In the CDM mechanism, the package substrate is charged to a positive or negative polarity and electrically isolated. The charged package is then discharged through the package external pins. Hence, a desired solution to establish a function of the regulator to allow current to bypass in an EOS/ESD event and prevent electrical destruction of the voltage regulator critical circuits.
The broad concept to allow current flow from one power rail to another is known. For example, in U.S. Pat. No. 5,079,612 to Takamoto et al., a subcircuit block is defined between separated Vcc power rails and Vss chip substrate rails. The intent is to make a short circuit through at least between one or two ground lines. Grounded gate n-channel transistors are used. In this implementation, there are no active elements to be protected between the Vcc power rails or between the Vss power rails.
In U.S. Pat. No. 5,124,877 to Graham, the technique of a discharge rail is disclosed. In this case, a bus is defined which has no voltage reference potential. In this application, only a single power supply voltage at the value of the value of the internal power rail Vdd is provided. The discharge rail is not connected to a second power supply. Additionally, there is no active circuitry between the first and second rails. Hence, there is no concern of a differential voltage between Vcc and Vdd when the chip is powered off.
The concept of gate coupling and triggerable circuits have been discussed between Vdd and ground Vss. In U.S. Pat. No. 4,423,431 to Sasaki, the technique of gate coupling on a MOSFET for ESD is disclosed. A resistor is placed in series with a receiver circuit. The resistor is followed by an n-type FET (NFET) connected between the input node and ground. The gate of the transistor is connected to the input node via a capacitor. In this implementation, the ESD impulse triggers the NFET via capacitance coupling, the ESD device being placed between the input node and ground.
In U.S. Pat. No. 5,255,146 to Miller, a pulse time network, on-time network and rise time network is used to feed a signal into an FET to establish a current discharge between Vdd and Vss chip substrate. In U.S. Pat. No. 5,287,241 to Puar et al., dynamic triggering is achieved between Vdd and Vss chip substrate by having an resistor/capacitor (RC) network turn on a p-type FET (PFET) placed between the two power rails. In U.S. Pat. No. 5,311,391 to Dungan et al., dynamic triggering is achieved using FETs in a diode-connected string between the Vdd and Vss electrodes. This diode-connected string acts as a level shifting network to initiate an RC network to turn on a MOSFET between Vdd and Vss. In U.S. Pat. No. 5,239,440 to Merrill, dynamic triggering is achieved using an RC network followed by two inverter stages and ESD logic which turns on the I/O buffers. In U.S. Pat. No. 5,237,395 to Lee, dynamic triggering is achieved between Vdd and Vss chip substrate by having an RC network turn on an NFET in series with a resistor placed between the two power rails. All of the above, pertain to the concept of triggerable ESD networks between the Vdd and Vss chip substrate to discharge to the ground plane. None of the above art addresses the case of multiple Vdd supplies and/or regulated environments where there is active circuitry between the Vcc and Vdd power rails where the Vdd is not connected to the external pin environment.
U.S. Pat. No. 4,853,416 describes the case where a regulator exists within the power grid structure of a semiconductor chip. In this case, the solution was not to allow current to flow into the internal Vdd power grid. A switch that is normally open is turned off when an over voltage event is sensed, thereby isolating the sensitive circuitry from the over voltage with the switch control provided by the inverter. This circuit avoids electrical overload to the voltage regulator and overload of the circuitry beyond the regulator. The Miller circuit uses resistor elements and a PFET to block the current to the regulated area.